AI/Deep learning Accelerator - Digital Design Verification Engineer
Andes Deep Learning Accelerator (AnDLA) is a highly efficient and cost-sensitive AI solution for edge devices and endpoints. AnDLA features hardwired processing units for matrix multiplication, convolution, pooling functions, and more in the future. You will develop functional verification infrastructure and create test patterns to ensure functional correctness of the AnDLA IP. You will develop test plans for various verification environments, such as self-check UVM environment and system-level verification with AndesCore processors. You will be involved in the AnDLA specification and micro-architecture discussion. You will work closely with the design engineers to ensure functional correctness. =================== Responsibilities =================== Verify for AnDLA IP. Build functional verification infrastructure, which includes various verification environments. Produce test plans and test patterns. Check the test coverage.公司地址:
新竹市公道五路三段1號10樓其他:
=================== Minimum qualifications =================== Master's degree in Electrical Engineering, Computer Science, or equivalent practical experience. Experience with UVM. Experience in functional verification, developing test plans and patterns. Experience with Verilog or SystemVerilog. Experience with C/C++ or other scripting languages such as Perl, Shell, Bash, etc. =================== Preferred qualifications =================== Knowledge of AI/deep learning accelerator IP design. Experience in formal verification using JasperGold. Experience in functional coverage.-2024-09-17