Silicon Design Engineer (Design)
THE ROLE: The focus of this role is to plan, build, and execute the design & integration of new and existing features for AMD’s IP, resulting in no bugs in the final design. THE PERSON: Good communicate skill, co-work spirit, strong self-learning and adaptability are preferring. KEY RESPONSIBILITIES: Responsible for IP Design/Integration Work as IP design/integration lead with potential grow to IP owner. Work with SOC/IP architect, IP vendor, system engineering team, and SW/FW teams to create IP features and define micro-architecture for client/server/embedded SOC products. Work on IP design/integration, LINT/CDC, Synthesis and Timing closure. Work closely with SOC team to ensure IP delivery meets with requirements. Work closely with SW, FW and system engineering teams on post-silicon bring-up/debug till production. Participate in IP/Company’s methodology improvement, and new technology/architecture definition. PREFERRED EXPERIENCE: Solid knowledge about AMBA, especially AXI. Experience in design or integrating high-speed IP is a must Solid x86 system architecture knowledge is a must Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Perl, Tcl and Ruby is a plus. Working knowledge/experience with SW driver and FW is a plus. Strong analytical/problem solving skills and pronounced attention to details. Self-motivated team player, and able to independently drive tasks to completion. Strong and clear communication skill, fluent in English are required. ACADEMIC CREDENTIALS: MSEE within 3 -8 years, or BSEE within 5-10 years’ experience on IP design/integration.公司地址:
台北市南港區經貿一路170號19樓 (台肥大樓 - 南港展覽館一館旁)其他:
歡迎領有身心障礙手冊或證明夥伴投遞履歷-2024-09-17