ASIC Design Verification Engineer

薪資範圍:待遇面議

公司名稱: 英屬開曼群島商愛康科技股份有限公司台灣分公司

Provide design verification services for our SoC ​※ Responsibilities: • Test bench development using System Verilog UVM • Test plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collections • Regression setup and debug at RTL level and gate sim level working with design team

公司地址:

新竹縣竹北市惟馨街95號13樓之5

其他:

​※ Requirements: • 10+ Design Verification experience • Deep knowledge about System Verilog, UVM and verification coverage matrix • Familiar with Synopsys PCIe/CXL VIP and Mentor Graphics QVIP • Strong experience with PCIe/CXL protocol (PHY/DLLP/TLP) • Very familiar with the peripheral protocols such as UART, I2C, SPI Flash • Proficient in Perl scripting ​※ English resume is required.-2024-09-17