Staff Design Verification Engineer
The Opportunity Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. Job Responsibilities: ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution. He/She will be responsible for block and /or chip level verification. The responsibilities include but not limited to. * Improve the design methodology and flow. * Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications. * Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines. * Provide the support to the product teams, for both pre and post silicon公司地址:
新竹縣竹北市其他:
Requirements: (1) MSEE with 6+ years of experience. (2) Good personal communication skills and team working spirit. (3) Hardworking and motivated to be part of a highly competent design team. Must be proficient in the following skills: * Fundamental concepts in digital logic design * Understand ASIC verification flows and methodologies * Verilog and SystemVerilog/SystemC/Vera * Strong Perl and Tcl scripting * UNIX Shell scripting (Csh, Bash) Highly desirable skills: * Formal verification * Low power design * MATLAB and C/C++ based system simulation and evaluation * DSP function hardware implementation knowledge-2024-09-17