Staff Digital IC Design Engineer_Central Engineering AMS
Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and /or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. • Improve the design methodology and flow. • Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. • Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. • Provide support to the product teams, for both pre and post-silicon公司地址:
新竹縣竹北市其他:
Master’s degree and/or PhD in EE, CS or related fields and 3+ years of experience. Good personal communication skills and team working spirit. Hardworking and motivated to be part of a highly competent design team. Must have good post-RTL experience including synthesis, timing analysis and physical design. Able to perform custom placement and routing for mixed-signal designs. Flexible to move between all post-RTL design activities as required. Good understanding of block and top-level physical timing closure. Must be proficient in the following skills: • Logic or physical synthesis using Synopsys or Cadence tools • DFT generation and verification • Static timing analysis using Primetime • Physical design for 28nm and beyond • Strong Perl and Tcl scripting skill Highly desirable skills: • Low power design • Circuit level or custom design experience • Floorplanning, clock-tree synthesis and power planning/analysis • Signal integrity and physical verification-2024-09-17