Staff Digital IC Design Engineer
*Write RTL code for Low power and multi-clock domain designs. *Perform synthesis and pre- and post-layout timing closure. *Run the whole front-end design flow such as Synthesis, power analysis, and Formal check etc. *Contribute test specifications and support evaluation of the design in coordination with application and product engineering. *Provide design documentation, descriptions and information to application engineers, field application engineers, products engineers, and customers.公司地址:
新竹縣竹北市其他:
*Major in EE, CS or related, Master's Degree with 2+ years or Bachelor's with 4+ years working experience in ASIC design. *Familiar with Verilog and RTL design *Good problem-solving and communication skills *Good written and spoken English. Be able to work together with the global team. *Familiar with System-Verilog and UVM verification methodology is a plus *Being Familiar with script languages (perl, tcl etc.) is a plus *Familiar with STA timing flow is a plus-2024-09-17